 [Saturn Core] Master Clock [message #5670] |
Mon, 17 September 2018 13:30  |
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I have a question about how master clock is handled in the core.
From what i Know for an NTSC System :
The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that.
When i read the source code i see :
const int32 MasterClock = PAL ? 1734687500 : 1746818182;
So i don't understand what corresponding to this frequencies.
[Updated on: Mon, 17 September 2018 13:30]
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| Re: [Saturn Core] Master Clock [message #5671 is a reply to message #5670 ] |
Mon, 17 September 2018 14:05  |
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| altair wrote on Mon, 17 September 2018 13:30 |
I have a question about how master clock is handled in the core.
From what i Know for an NTSC System :
The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that.
When i read the source code i see :
const int32 MasterClock = PAL ? 1734687500 : 1746818182;
So i don't understand what corresponding to this frequencies.
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From where did you get 1708 and 1820? Anyway, 1708/1820 = 61/65
enum
{
CLOCK_DIVISOR_26M = 65,
CLOCK_DIVISOR_28M = 61
};
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| Re: [Saturn Core] Master Clock [message #5673 is a reply to message #5671 ] |
Mon, 17 September 2018 14:40 |
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Ah now i understand.
1746818182 correspond to a virtual master clock frequency allowing you to use integer divider 
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