| Question about the VDC latch [message #657] |
Thu, 08 February 2007 19:00  |
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Looking through the Spriggan Mark 2 code, it appears as if each of the VDC regs has its own latch/buffer.
Spriggan Mark 2:
- store the working reg to zeropage address buffer, before writing to the VDC
- preceed to write to the other regs, i.e. $00 and $02
- interrupt occurs during the transfer, changes reg to $07 or $08, writes to the VDC, then restores VDC reg from zeropage buffer
When the interrupt happens between writing to $0002 and $0003, it does not appear to corrupt the latch when returning from interrupt. Is this correct?
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| Re: Question about the VDC latch [message #658 is a reply to message #657 ] |
Thu, 08 February 2007 19:01  |
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The VRAM write latch is specific to VDC register $02 (VWR) and not the $0002 or $0003 data ports. When you access $0002 or $0003, you are directly accessing the register selected by $0000, instead of any temporary storage.
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