| VDC and screensize & nits [message #675] |
Thu, 08 February 2007 19:16  |
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Right.. maybe some VDC guru knows details of the formulas used to calculate correct values for odd display sizes (like 352x240 or 240x192.. don't ask why). I mean the VDC registers HSR, HDR, VPR, VDW and VCR. I went through various sources and the information seems not to be too consistent 
Also what's the correct use of MWR's CM bit?
Thanks!
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| Re: VDC and screensize & nits [message #676 is a reply to message #675 ] |
Thu, 08 February 2007 19:16  |
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When the VRAM dot width field (bits 1,0) of MWR are set to 11b, the VRAM bandwidth is so reduced that the VDC only reads bitplanes 0,1 *or* bitplanes 2,3 from VRAM for each tile, reducing the per-tile color count to four colors total (2bpp graphics).
The CM bit says which bitplanes are read; 0= bitplanes 0,1 (2,3 assumed to be zero) and 1= bitplanes 2,3 (0,1 assumed to be zero)
Note that the relative positions of bitplane data are still maintained; a tile using bitplanes 0,1 uses colors 0,1,2,3 from a palette, a tile using bitplanes 2,3 uses colors 0,4,8,C from a palette.
You can change the CM bit on a per-scanline basis. I used it in my interlace demo to pack two 2bpp 512x224 images into a tile set and display either one.
Gotta add this to the wiki and make an example program. 
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| Re: VDC and screensize & nits [message #677 is a reply to message #675 ] |
Thu, 08 February 2007 19:16 |
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Now this is interesting.. What VRAM dot width values 01b and 10b do? (Can't test stuff now unfortunately.. kids stole my hw to their gaming sessions  )
Then one more mysterious register.. VCE control register. What does its bit 0 (color clock frequency?) do? Magickit library.asm seems to set it differently depending on the x-resolution?
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| Re: VDC and screensize & nits [message #678 is a reply to message #675 ] |
Thu, 08 February 2007 19:17 |
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The dot width fields for both the backgrounds and sprites are used to allow slower VRAM bandwidth, if you were using slow SRAMs or DRAMs. To the programmer, there is no big change. All incarnations of the PCE hardware have fast (100ns) SRAM.
The 00b setting is special just because the bandwidth is so reduced that the # of bitplanes read per background tile or sprite is halved.
Actually when using the 512-pixel screen widths you'd probably want to use anything but the fastest settings (11b for either field) because otherwise the VDC access VRAM faster than it can be done. In practice, I've never noticed any VRAM corruption as a result (it's only about 10% faster than the chips are rated for)
VCE control register:
Bits 1,0 = Set screen width (0=256 pixels, 1=352 pixels, 2,3=512 pixels)
Bit 2 = Frame height (0= 262, 1= 263 scanlines)
Bit 7 = Color subcarrier enable (0= enabled, 1= disabled (B&W video))
Once the screen width has been set, then the VDC's registers like HDR, HSR, etc. are set up to center the display. For example some games use the 352-pixel mode and center a 320-pixel screen in the middle.
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| Re: VDC and screensize & nits [message #679 is a reply to message #675 ] |
Thu, 08 February 2007 19:17 |
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Thanks a lot for this great info!! Just nit picking related to your latest posting. The fastest dot width setting is 00b and the slowest is 11b (and not the other way around), right?
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| Re: VDC and screensize & nits [message #680 is a reply to message #675 ] |
Thu, 08 February 2007 19:17 |
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11 is the fastest, 00 is the slowest. I wrote an article about it here:
http://pcedev.mednafen.com/lick/HuC6270#Character_cycles
You can use 11b all the time, though I mention a case where it could cause trouble.
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| Re: VDC and screensize & nits [message #681 is a reply to message #675 ] |
Thu, 08 February 2007 19:18 |
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Charles, the VRAM(sram) chips on both SGX units and (US) Duo I have are -12. I was assuming 12ns since it was SRAM, but I realized the date of the machine would probably mean it is 120ns as some ram companies chips abreviated it like so. The system ram is -10. Still, 120/100ns sounds really slow for SRAM. So Was DRAM in the ~250/300ns range in that time period?
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